Open Source Minicomputer (Updated 2024/02/20)

marc · 2021-01-03 18:59:25

Gentle friends,

First, let me thank you all for your efforts and thoughts in many lanes towards the eventual placement of some of Earths' species on Mars. Thank you also for all your ideas and interest in the work I am doing.

I have to keep my posts here brief, because time in my lab is precious. I'll hit a couple of ideas I picked out in what you have said.

SpaceNut, about the "and, or, nand, etc. ... of the late 70's," I do love all that hardware. 2-input NAND gates like TI's SN74AUC1G00xxx can switch in about a nanosecond, and some gates like these arrive in my design at critical points. But we need more transistors if we're going to build a machine with (a) memory, and (b) non-toy computing operations. The system I'm designing will have on the order of a billion transistors, not including the NOR flash chip that the firmware will be loaded from.

tahanson43206 and I probably met in the mid-1980s. Some of his comments. Firsts, an "architypal" chip in my machine would be a 256k x 18-bit synchronous RAM such as GSI's GS840Z18CGT-250I. 18 bits in, 18 bits out, answer 5.5 ns after the clock pulse. A couple ns setup time ahead of the clock is needed. The present ALU design has about 20 of these. These go w-a-a-y beyond AND, OR, NAND, etc.

I am not worried about this idea not being "good enough for someone." This machine is for the 1% of the 1%, and I know that. But we're important, and this is the machine we need. Many would never bother to do what is needed to adapt to what I have proposed and am in the process of building.

tahanson43206 heard more recently that I am not "open to" seeking grants. It is my policy to apply for grants, as I have applied in the past, and to continue applying when not funded. Please all keep me in your good thoughts, because a decision is anticipated on a vital one in Q1 2021.

About virtual environments to run on this machine, it's not going to happen. All these "modern" platforms are /so/ bug-infested and complex. Also, as mentioned, there is no DRAM in the system. Only SRAM, which costs about 600 times more than DRAM at recent prices. And the packages are small; I haven't seen chips larger than 576 Mbit on the market as yet.

Realistically the first language will indeed be assembly language, a somewhat strange one. Stay tuned, because there's a solid start on the manual for the assembler, and it should be about finished sometime this spring. The second will be a scripting language written in the assembler, maybe a little like Python, but with a much smaller set of library features. The assembler itself is substantially written, and is waiting for some hardware details to be ironed out before it can be extended further. I can't decide what the instructions are until I know very exactly what the machine can do.

kbd512, I think it might be cheaper and logistically simpler to shield a 500 gram machine than to build a 50 (or 500) kilogram machine for use on Mars. Humans have a lot of machine-years of experience computing on Mars already, and it seems to be going rather well. I'm designing my CPU for ... sorry ... -40 C to +85 C, but that's without adding some of the cool enclosures that have appeared in this forum. Getting to what y'all call "250 F" (no one on Mars should use the F word) is long-ago accomplished, and parts for my system are available with that spec. But the CPU does have to run slower, because speeds are derated on the automotive and military temperature parts.

The 3-layer ALU design is a mature thing, and you can download a full implementation (as a simulation) today and run programs on it. The rest of the CPU is where I am focused at this time, and as we move into the spring, it too will be something that can be downloaded and run as a simulation. Sometime this summer, it's my hope that you can download Gerber files for circuit boards of early working implementations.

In the meantime there is a LOT do do, and I need to scoot for the moment. Happy New Year to each of you.

Marc

SpaceNut · 2021-01-03 19:27:46

First welcome to newmars...Good to hear from you and while I might not fit for the level you are in computers they do not phase me as I have seen most forms or another into asic large scale and then some. I spent time in a component disk r&d lab prototyping chips with chips and more.
That's enough about me and glad to see the work in time. Keep in mind heat removal and energy used is also as much in the priority of importance as mass is.

kbd512 · 2021-01-09 02:38:47

Marc,

Welcome to the New Mars Forums. We're happy to have you as a member.

While I recognize that we can run small disposable special purpose computers using rad-hard processors, those are also absurdly more expensive than SRAM chips. The new Cortex ARM chips may be more affordable, but I don't know how much they actually cost since we're still experimenting with them. I'm guessing those aren't particularly cheap, either. To the extent that I understood what I was read about the design used in Curiosity, they have more processing capability built into the chip than they actually require and they deal with the soft and hard faults encountered through redundancy or acceptance of aberrant behavior or diminished computing capabilities associated with the high background radiation environment and large temperature swings. The computer in Curiosity has a RHU, as did the Spirit and Opportunity rovers.

Curiosity has a pair of computers running 200MHz RAD750 chips, 256kB EEPROM, 256MB DRAM, and a 2GB SSD. Those computers cost $200K each, but one of them failed in less than a year. That might not be a particularly dangerous event for a robotic mission, but a human living on Mars for the rest of his or her life may disagree. I'd think that $400K would buy quite a few SRAM chips. Mouser says I can buy 967 400MHz 144MB SRAM chips for the same amount of money. I would think that with 139GB worth of SRAM, or thereabouts, we could probably build a reasonably powerful computer. I think the new RAD5545 chips have a 466MHz clock speed and Cortex is promising 500MHz clock speeds.

The 110 to 1,100 pounds of packaging was mostly heat sink and radiation shielding mass. I make a habit of using the F-word to upset the fragile sensibilities of our new-age C-word users. Anyhow, I wasn't suggesting that the chips had to withstand +/-250F , merely that the computer had to function in an Earth orbital environment and Mars orbital environment using a combination of radiation and climate control components (encasing the chips in a large block of metal) to enable the computer to function in that environment.

The overarching goals were to produce a fault tolerant machine capable of many years of continuous operation in a hostile environment, to reduce the number of different types of electronic components, and to use commercial chips, rather than military / aerospace chips. I'm sure BAE makes excellent hardware, but we're probably not selling many of them to unapproved users or users who don't have exceptionally deep pockets. SpaceX maximizes use of commercial technology to reduce development and operational costs, for example.

tahanson43206 · 2021-01-09 08:05:15

For kbd512 re #350

marc does not monitor this forum, so I'll forward a link to your post.

Edit#1: The link was forwarded.

Considering marc's schedule, it seems reasonable (to me at least) to expect a delay between receipt and reply.

In the meantime, this topic is available for anyone else in the Registered Membership who has some knowledge of computer hardware design to contribute to the flow here. There are a few folks still living on Earth who have been involved in design of a CPU from the ground up, and some of that work has been documented. A notable example is Prime Computer, but I wasn't able to find the book I am remembering.

In case anyone might be interested in one phase of early computing, a web site called "historyofcomputercommunications.info" has an article about Prime Computers (7.2-Prime). I was not aware of some of the history recorded there.

In the present instance, we have a person who has decided to design a computer architecture from the ground up, and we (forum members and readers) have a chance to follow along and (perhaps) even to take part in construction of a working CPU and in development of software.

In thinking about this recently, I realized that the best candidate for interfacing the new computer to the rest of the world is the USB protocol.

A reference I have on hand (and which I can recommend) is: "USB Complete" by Jan Axelson (I have the 4th Edition) There are later editions.

What I decided after considering writing a USB interface for a hardware project was that (in my case) it would make sense to adopt an existing peripheral and write code to interact with it, rather than to go through all that would be required to create a new special purpose peripheral.

However, Jan's detailed documentation gave me the impression I could have pulled it off if I'd been willing to do so.

In the case of the new CPU architecture under development in this case, there is no way around the need to write the BIOS level drivers for a USB interface.

Someone needs to take that on, since the primary developer is totally absorbed in designing the assembler commands to match the hardware as it develops.

Whoever takes this on would be investing time in an enterprise with an uncertain future. The only certainty is that such a person would master USB specifications at the most basic level, and thus would be immensely valuable to any of hundreds if not thousands of companies around the world who are developing products to meet the USB specifications.

For kbd512 ... in your case, it might will turn out that you know a young person with the capability of designing such a USB interface for a new architecture.

I would be happy to (try to) arrange a flow of communication between the prime developer and your candidate, if one becomes available.

(th)

SpaceNut · 2021-01-09 11:14:27

The other thing which I remember from processor use is the reduced instruction set types (risc) which do have unique design applications attached to them. As for hardening thats all done at the semiconductor levels as a function of component build with the materials and laying types.

tahanson43206 · 2021-01-09 11:54:46

For SpaceNut re #352

Thanks for adding RISC to the discussion, and a reminder of where radiation hardening can take place.

In the present instance, since the CPU design is under construction from scratch, there were NO instructions to start with, let along a Reduced set.

It will definitely be interesting to see what machine language commands marc comes up with. He said he is still developing the hardware, and adding assembler level instructions to tell the hardware to perform functions. I haven't seen the code for ** this ** machine, but I've seen a lot of assembler language variations. We can expect the primary arithmetic operations, moves of various kinds, shifts of various kinds and perhaps others that forum members can remember working with, or which they can call up from wikipedia or other resources.

The company I was trying to remember earlier, in a reply to kbd512, was Tandem Computers.

Wikipedia has a comprehensive article on them.

I asked Google for a book about Operating System design and received back an impressive (to me for sure) list of offerings.

(th)

SpaceNut · 2021-01-09 14:45:06

Having worked in the 80s for computer manufacturing that had proprietary OS, designed AOS for the military, made use of unix or linx and many more that came back to the processor instruction set and the compilers for them to work for what programming language was used to write the assembly language for the machine to use. This further goes up the networking design as the commands are still based on the components that are used to send and receive the information that is coming from the computer to the next computer.

tahanson43206 · 2021-01-10 07:16:39

For kbd512 ... marc read your post. To my surprise, he seems to have liked it. Reply will be "eventual".

From my perspective (trying to encourage folks to assist with the forum mission) I appreciate your taking an interest in the CPU design project.

I can't tell if this is a seed for an industry, or something less than that. I ** do ** like the idea of Mars settlers being able to achieve independence from Earth sooner rather than later, by being able to fabricate less complex chips on site than is the state-of-the-art on Earth.

The Mars Convention videos about the City-State competition are quite interesting (to me for sure). The last one (I think it is #36) includes forecast of gradual introduction of high density silicon etching. The end state in their vision is equivalence with Earth. That could certainly happen, but I'm interested in the early stage, between initial exploration and "just survival" and the 1,000,000 person end state.

This is Technology Updates topics ... it is a good place for marc's project to start, but I'd prefer we (Admins and Moderators) agree on a more appropriate topic at some point.

It's probably difficult to define a suitable topic title at this point, so I'll let it ride for now. At some point, I'd like future forum readers to be able to follow the flow of discussion about this new architecture from the top without a lot of digressions, interesting as they may be.

(th)

SpaceNut · 2021-02-26 19:32:50

marc wrote:

Hi SpaceNut and friends,
The progress (th) attributes to me is slightly in advance of our time. I anticipate that this will be the world's most open minicomputer architecture, and arguably the most secure.
When we say "layout," we usually refer to a circuit board that is ready for production. What I have is a component placement for the purpose of estimating wire length and capacitance, to feed into a simulation that can verify logic and timing. Now yes, I think the graphic (th) has seen showing proposed part relationships is cool, as well as the wiring approximation which he has not seen. In fact, a careful glance shows the wiring to be wholly ludicrous, until you understand that it was not for routing. But "completed layout," I cannot claim.
There is a list of parts that go on the board amounting to $414 in small quantities at current prices, although I have functionality yet to add. It's true that an assembler exists, and that more will be added to the assembler as I better understand how certain operations will happen in hardware.
I claim no readiness for "detailed review," or that I am "looking for help" therewith. Although within a year, I will welcome audits by people who would like to challenge the security of the architecture.
My interest in finding grant funds is subject to the outcome of a pending application. Stay tuned, and thanks all!
Marc

SpaceNut wrote:

I have built boards as complex as that and then some in point to point wiring as well as with single to multiple layer with micro via's. Have done pcb layouts for smd parts using photo reduction and resists so what you have shown seems typical of both layout of component placement and routing of connections. Many forget that parallel paths can have crosstalk between runs and they also forget that length difference cause missing bits hen looking at timing.

SpaceNut · 2021-02-26 19:33:18

tahanson43206 wrote:

For SpaceNut re #850
Would you be interested in building one of these CPU's, when Marc is ready for that step.
One build method that occurs to me as we wait for the design to reach assembly stage is the (decidedly ancient) wire wrap method. I remember seeing production equipment made by running wires from prongs under the chip mount surface. I expect the actual wiring is done under computer control, similar to how a 3D Printer moves to position the extrusion head to deliver a dab of liquefied plastic. A wire wrap robot (if any still exist) would move under computer control from one pin to another, stretching an insulated wire between the pins. Using that method, the complexity of dealing with circuit board layout is eliminated entirely.
This design is for a slow, inexpensive, ultra-reliable computer that can be build and maintained on Mars.
Edit#1: I asked Google about 36 bit computers, and since there is quite a history, Google had a lot of citations to offer. A question that pops up (from scanning the citations) is what is the address bus of Marc's design? The size of the address bus determines the amount of physical memory.
In addition, again from a quick scan of the citations, I'm wondering what the word size ... apparently early designs had 6 bit words.
I see a familiar number in the citations ... 32 bit machines have an address space of 4,294,967,296 bytes. Since I have a mix of 32 bit and 64 bit machines, and since FAT formatting is still common on USB devices, I often see a limit of 4 Gb in file size, that can be solved by converting the USB format to NTSF.
I asked Google about 36 bit computers and got 68,719,476,736 as the 36th power of 2. That would imply a 36 bit computer could directly access 68 Gb.
Presumably 36 Gb would be a decent memory capability for a computer for a while.
Another quick check with Google revealed that a high end gaming machine may have 32 Gb of RAM today.
Edit#2: Here is a link to a wire wrap prototyping board (I ** think ** that's what it is)...
https://www.digikey.com/en/products/det … gLXavD_BwE
Edit#3: Here is what I am remembering ... if the image works, it is of a Z80 on a wire-wrap prototyping board:
https://www.google.com/url?sa=i&url=htt … AdAAAAABAD
If the link above works for you (forum reader) the article is a story about working on a Z80 prototype and having an intermittent problem caused by a small length of snipped wire wrap wire that fell into the "rat's nest". The comments go on at some length, remembering similar incidents.
I came away with an appreciation for why printed circuit boards became routine and then standard. I've had a single layer (very simple) board made, and noted that the company can make multilayered boards for those who need them.
Still, the first working version of the CPU under development by Marc might well happen on a wire wrap prototyping board.
(th)

SpaceNut · 2021-02-26 19:33:59

marc wrote:

I think you would like some of the circuit board prototyping capability that has come available in recent years. I recently did a lot of legwork to help someone pick out equipment for a microelectronics makerspace. It's not lightweight machinery, but I think it's worth sending. I don't anticipate problems soldering on Mars, although fumes should be contained.
The COTS components in this design aren't suitable for sockets, so wire wrap would not be a straightforward solution. There's also a synchronization problem, in that the flip-flops' clock inputs can't be synchronized neatly with the RAM clock inputs. This eats into a 2 nanosecond window before the data we're trying to clock is lost, and wire wrap will be more difficult to control.
There also isn't a very solid ground plane for wire wrap, which I think is going to be rough on a few fronts.
Once I am comfortable with logic, timing, and coverage, assembling the first board should be a breeze. I've already obtained more than 90% of the components that have already been decided on.
I've been planning to use KiCad to route tracks, and I'm not sure whether it will fare well with this many pins. Simply opening a board with the parts placed and dragging them seems to be straining the program. SpaceNut, suggestions? I realize that a commercial CAD tool might help me on one hand, but it would also reduce the architecture's legitimacy as open hardware.
Another image is available now.
Let's talk about RAM. This board will accept at most 8M x 36 bits for data, and 4M x 36 for code, and that's all. SRAM chips don't hold many bits relative to other memory types, especially if they happen to have gull-wing leads that can be hand soldered or checked by flying probe testers after delivery. It's starting to look like I have some extra breathing room for bus timing, so I might be able to double up on the number of RAM chips later.
As for the architecture, I would ordinarily say the address space is 27 bits. This is definitely true for code, because all branches have their destination within the 36-bit instruction. So with a 9-bit opcode, 27 bits are left for where to branch to. For security reasons, there are no indirect branches, so I'm not taking requests to change this. For those who think that a system needs to hold more than 128M words of code, my answer is that 128M is already too many, since there is no sound way to do a security audit on a program that large. (No, you CAN'T automate malware scans, as Henry Gordon Rice proved in 1952. There are, of course, a lot of companies that pretend to do so.)
For the data, I've assumed the address space is 27 bits, but we might bring that up to 36 bits. It's on you to talk someone into making the RAMs, though.

SpaceNut · 2021-02-26 19:34:34

tahanson43206 wrote:

For marc re #853 ...
Thank you for clarifying a number of points, including the question of wire wrap ....
May I inquire if it might be time to open a dedicated topic? You are a welcome guest in Housekeeping, but that topic is intended (and is used) primarily for administrative traffic.
You have the ability to create a topic of your choosing, and the moderators are available to help you manage it if you find something contributed that is not a good fit.
I am interested in trying a concept for a parallel topic for folks to make comments without intruding on the flow of the primary topic.
(th)

SpaceNut · 2021-02-26 19:39:49

Well I no longer have any tools to build with but it would have still been a challenge to build it operationally.

There are draw backs to wire wrap circuit build in terms of the cross talk in busses, timing due to wire lengths but each socket for the wrap to go onto is typically in the 5 - 10 pf capacitance which is then a problem with speed.

tahanson43206 · 2021-02-26 20:50:08

For SpaceNut re this new topic!

Nice work! I hope this topic thrives!

(th)

marc · 2021-02-27 11:32:42

Hi all! I think it was a good idea to split this thread off for better navigation and focus by all affected. Thanks to (th) for all the efforts in this direction.

You can tell I have something that is hard for me to bring up, in light of all this effort. I'm happy to post to this thread as appropriate, but a disclaimer is warranted. I am not designing or constructing a microprocessor. I don't know how readily categories can be renamed, but if the alteration isn't onerous, I might suggest "Open Source Minicomputer." Here is my reasoning. First, I regard a microprocessor as fitting on one die. (Early microprocessors sometimes needed more than one die, but we're no longer there.) CPU is not a good substitute term, because it's not nearly enough to build a CPU.

Of course I don't expect everyone to use the same terms I do consistently, and were this not a category heading created with my work in thought, it wouldn't have been necessary to bring this up. But since I'm writing, here are some other terms that I sometimes use, and how I have defined these terms in earlier writing:

Complex logic. Sequential circuitry of sufficient complexity to be capable of concealing exploitable defects.

Discounted logic. Logic for which a documented risk assessment and other controls validly establish that exploitable defects are unlikely to exist.

Maker-scale assembly tools. Tools and methods for constructing electronics that are within economic reach of most technically qualified builders.

Microcomputer. From convention and (*), a “computer system that utilizes a microprocessor as its central control and arithmetic element.”

Minicomputer. A computer where all complex logic, including but not limited to the central processing unit, that is not discounted is solder-defined.

Primary storage. Memory that a CPU accesses via load and store instructions. Primary storage is what people usually mean when they say “RAM.”

RAM. Unless otherwise stated, another term for static RAM. In my architecture, most SRAM is not primary storage, but implements logic or registers.

Solder-defined behavior. Operational behavior that is determined by solder-defined hardware.

Solder-defined hardware. Circuitry that can be assembled from a set of components containing no complex logic, using maker-scale assembly tools.

Supply-chain firewall. A point in a supply chain through which one or more classes of exploitable defects will not readily pass.

(*) Andrew Butterfield et al., eds. 2016. A Dictionary of Computer Science (7th ed.). Oxford University Press, Oxford, England.

Marc

Last edited by marc (2021-02-27 11:36:01)

SpaceNut · 2021-02-27 12:11:57

sorry Marc, to not be able to change the title as the software mode is not installed....

I think your posts sets the tone of the topic going forth that its more than just one part...that its the complete assembly that you are working towards.

SpaceNut · 2021-03-05 21:23:13

why-the-mainframe-is-alive-and-thriving

SpaceNut · 2024-02-19 14:15:05

Making things computer in nature requires Chip makers and software program creation.

Currently almost no components are made on US soil and under Covid a renewed effort was started but most just tried to set up small offices with foreign makers with hidden intensions.

Good to see an effort is still happening Largest US semiconductor maker snags $1.5B from stalled Chips Act for plants in NY, Vermont

The Biden administration awarded $1.5 billion to the nation’s largest domestic semiconductor manufacturer — the first major grant from the $52 billion Chips Act passed nearly two years ago.
GlobalFoundries, the world’s third-largest contract chip maker, will build a new semiconductor production facility in Malta, NY, as well as expand existing operations at the plant and another in Burlington, Vt., according to a preliminary agreement with the Commerce Department.
The grant will be accompanied by $1.6 billion in available loans, with the funding expected to generate $12.5 billion in overall potential investment across the two states.
“The chips that GlobalFoundries will make in these new facilities are essential chips to our national security,” Commerce Secretary Gina Raimondo told reporters at a briefing.
GlobalFoundries intends to use the funding to help pay for the construction of a new advanced chip factory in Malta, located about 30 miles north of Albany. It will also increase production at the existing plant in Malta as part of a strategic agreement with General Motors, and revitalize its plant in Burlington, Vermont.
In August 2022, Biden signed the bipartisan CHIPS Act to bolster domestic production of semiconductors to hedge against China’s saber-rattling aimed at Taiwan — a key supplier of the world’s advanced computer chips.

A safeguard to Chinese invasion...

Thus far, the government has awarded just a $35 million grant to BAE Systems to increase production at a New Hampshire factory making chips for military aircraft, including F-15 and F-35 jets.
In December, Samsung, the Korean electronic giant, announced that it would delay production at its new chip manufacturing plant in Texas until 2025.

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#26 2021-01-03 18:59:25

Re: Open Source Minicomputer (Updated 2024/02/20)

#27 2021-01-03 19:27:46

Re: Open Source Minicomputer (Updated 2024/02/20)

#28 2021-01-09 02:38:47

Re: Open Source Minicomputer (Updated 2024/02/20)

#29 2021-01-09 08:05:15

Re: Open Source Minicomputer (Updated 2024/02/20)

#30 2021-01-09 11:14:27

Re: Open Source Minicomputer (Updated 2024/02/20)

#31 2021-01-09 11:54:46

Re: Open Source Minicomputer (Updated 2024/02/20)

#32 2021-01-09 14:45:06

Re: Open Source Minicomputer (Updated 2024/02/20)

#33 2021-01-10 07:16:39

Re: Open Source Minicomputer (Updated 2024/02/20)

#34 2021-02-26 19:32:50

Re: Open Source Minicomputer (Updated 2024/02/20)

#35 2021-02-26 19:33:18

Re: Open Source Minicomputer (Updated 2024/02/20)

#36 2021-02-26 19:33:59

Re: Open Source Minicomputer (Updated 2024/02/20)

#37 2021-02-26 19:34:34

Re: Open Source Minicomputer (Updated 2024/02/20)

#38 2021-02-26 19:39:49

Re: Open Source Minicomputer (Updated 2024/02/20)

#39 2021-02-26 20:50:08

Re: Open Source Minicomputer (Updated 2024/02/20)

#40 2021-02-27 11:32:42

Re: Open Source Minicomputer (Updated 2024/02/20)

#41 2021-02-27 12:11:57

Re: Open Source Minicomputer (Updated 2024/02/20)

#42 2021-03-05 21:23:13

Re: Open Source Minicomputer (Updated 2024/02/20)

#43 2024-02-19 14:15:05

Re: Open Source Minicomputer (Updated 2024/02/20)

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