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Hi all! I think it was a good idea to split this thread off for better navigation and focus by all affected. Thanks to (th) for all the efforts in this direction.
You can tell I have something that is hard for me to bring up, in light of all this effort. I'm happy to post to this thread as appropriate, but a disclaimer is warranted. I am not designing or constructing a microprocessor. I don't know how readily categories can be renamed, but if the alteration isn't onerous, I might suggest "Open Source Minicomputer." Here is my reasoning. First, I regard a microprocessor as fitting on one die. (Early microprocessors sometimes needed more than one die, but we're no longer there.) CPU is not a good substitute term, because it's not nearly enough to build a CPU.
Of course I don't expect everyone to use the same terms I do consistently, and were this not a category heading created with my work in thought, it wouldn't have been necessary to bring this up. But since I'm writing, here are some other terms that I sometimes use, and how I have defined these terms in earlier writing:
Complex logic. Sequential circuitry of sufficient complexity to be capable of concealing exploitable defects.
Discounted logic. Logic for which a documented risk assessment and other controls validly establish that exploitable defects are unlikely to exist.
Maker-scale assembly tools. Tools and methods for constructing electronics that are within economic reach of most technically qualified builders.
Microcomputer. From convention and (*), a “computer system that utilizes a microprocessor as its central control and arithmetic element.”
Minicomputer. A computer where all complex logic, including but not limited to the central processing unit, that is not discounted is solder-defined.
Primary storage. Memory that a CPU accesses via load and store instructions. Primary storage is what people usually mean when they say “RAM.”
RAM. Unless otherwise stated, another term for static RAM. In my architecture, most SRAM is not primary storage, but implements logic or registers.
Solder-defined behavior. Operational behavior that is determined by solder-defined hardware.
Solder-defined hardware. Circuitry that can be assembled from a set of components containing no complex logic, using maker-scale assembly tools.
Supply-chain firewall. A point in a supply chain through which one or more classes of exploitable defects will not readily pass.
(*) Andrew Butterfield et al., eds. 2016. A Dictionary of Computer Science (7th ed.). Oxford University Press, Oxford, England.
Marc
I think you would like some of the circuit board prototyping capability that has come available in recent years. I recently did a lot of legwork to help someone pick out equipment for a microelectronics makerspace. It's not lightweight machinery, but I think it's worth sending. I don't anticipate problems soldering on Mars, although fumes should be contained.
The COTS components in this design aren't suitable for sockets, so wire wrap would not be a straightforward solution. There's also a synchronization problem, in that the flip-flops' clock inputs can't be synchronized neatly with the RAM clock inputs. This eats into a 2 nanosecond window before the data we're trying to clock is lost, and wire wrap will be more difficult to control.
There also isn't a very solid ground plane for wire wrap, which I think is going to be rough on a few fronts.
Once I am comfortable with logic, timing, and coverage, assembling the first board should be a breeze. I've already obtained more than 90% of the components that have already been decided on.
I've been planning to use KiCad to route tracks, and I'm not sure whether it will fare well with this many pins. Simply opening a board with the parts placed and dragging them seems to be straining the program. SpaceNut, suggestions? I realize that a commercial CAD tool might help me on one hand, but it would also reduce the architecture's legitimacy as open hardware.
Another image is available now.
Let's talk about RAM. This board will accept at most 8M x 36 bits for data, and 4M x 36 for code, and that's all. SRAM chips don't hold many bits relative to other memory types, especially if they happen to have gull-wing leads that can be hand soldered or checked by flying probe testers after delivery. It's starting to look like I have some extra breathing room for bus timing, so I might be able to double up on the number of RAM chips later.
As for the architecture, I would ordinarily say the address space is 27 bits. This is definitely true for code, because all branches have their destination within the 36-bit instruction. So with a 9-bit opcode, 27 bits are left for where to branch to. For security reasons, there are no indirect branches, so I'm not taking requests to change this. For those who think that a system needs to hold more than 128M words of code, my answer is that 128M is already too many, since there is no sound way to do a security audit on a program that large. (No, you CAN'T automate malware scans, as Henry Gordon Rice proved in 1952. There are, of course, a lot of companies that pretend to do so.)
For the data, I've assumed the address space is 27 bits, but we might bring that up to 36 bits. It's on you to talk someone into making the RAMs, though.
Hi SpaceNut and friends,
The progress (th) attributes to me is slightly in advance of our time. I anticipate that this will be the world's most open minicomputer architecture, and arguably the most secure.
When we say "layout," we usually refer to a circuit board that is ready for production. What I have is a component placement for the purpose of estimating wire length and capacitance, to feed into a simulation that can verify logic and timing. Now yes, I think the graphic (th) has seen showing proposed part relationships is cool, as well as the wiring approximation which he has not seen. In fact, a careful glance shows the wiring to be wholly ludicrous, until you understand that it was not for routing. But "completed layout," I cannot claim.
There is a list of parts that go on the board amounting to $414 in small quantities at current prices, although I have functionality yet to add. It's true that an assembler exists, and that more will be added to the assembler as I better understand how certain operations will happen in hardware.
I claim no readiness for "detailed review," or that I am "looking for help" therewith. Although within a year, I will welcome audits by people who would like to challenge the security of the architecture.
My interest in finding grant funds is subject to the outcome of a pending application. Stay tuned, and thanks all!
Marc
Gentle friends,
First, let me thank you all for your efforts and thoughts in many lanes towards the eventual placement of some of Earths' species on Mars. Thank you also for all your ideas and interest in the work I am doing.
I have to keep my posts here brief, because time in my lab is precious. I'll hit a couple of ideas I picked out in what you have said.
SpaceNut, about the "and, or, nand, etc. ... of the late 70's," I do love all that hardware. 2-input NAND gates like TI's SN74AUC1G00xxx can switch in about a nanosecond, and some gates like these arrive in my design at critical points. But we need more transistors if we're going to build a machine with (a) memory, and (b) non-toy computing operations. The system I'm designing will have on the order of a billion transistors, not including the NOR flash chip that the firmware will be loaded from.
tahanson43206 and I probably met in the mid-1980s. Some of his comments. Firsts, an "architypal" chip in my machine would be a 256k x 18-bit synchronous RAM such as GSI's GS840Z18CGT-250I. 18 bits in, 18 bits out, answer 5.5 ns after the clock pulse. A couple ns setup time ahead of the clock is needed. The present ALU design has about 20 of these. These go w-a-a-y beyond AND, OR, NAND, etc.
I am not worried about this idea not being "good enough for someone." This machine is for the 1% of the 1%, and I know that. But we're important, and this is the machine we need. Many would never bother to do what is needed to adapt to what I have proposed and am in the process of building.
tahanson43206 heard more recently that I am not "open to" seeking grants. It is my policy to apply for grants, as I have applied in the past, and to continue applying when not funded. Please all keep me in your good thoughts, because a decision is anticipated on a vital one in Q1 2021.
About virtual environments to run on this machine, it's not going to happen. All these "modern" platforms are /so/ bug-infested and complex. Also, as mentioned, there is no DRAM in the system. Only SRAM, which costs about 600 times more than DRAM at recent prices. And the packages are small; I haven't seen chips larger than 576 Mbit on the market as yet.
Realistically the first language will indeed be assembly language, a somewhat strange one. Stay tuned, because there's a solid start on the manual for the assembler, and it should be about finished sometime this spring. The second will be a scripting language written in the assembler, maybe a little like Python, but with a much smaller set of library features. The assembler itself is substantially written, and is waiting for some hardware details to be ironed out before it can be extended further. I can't decide what the instructions are until I know very exactly what the machine can do.
kbd512, I think it might be cheaper and logistically simpler to shield a 500 gram machine than to build a 50 (or 500) kilogram machine for use on Mars. Humans have a lot of machine-years of experience computing on Mars already, and it seems to be going rather well. I'm designing my CPU for ... sorry ... -40 C to +85 C, but that's without adding some of the cool enclosures that have appeared in this forum. Getting to what y'all call "250 F" (no one on Mars should use the F word) is long-ago accomplished, and parts for my system are available with that spec. But the CPU does have to run slower, because speeds are derated on the automotive and military temperature parts.
The 3-layer ALU design is a mature thing, and you can download a full implementation (as a simulation) today and run programs on it. The rest of the CPU is where I am focused at this time, and as we move into the spring, it too will be something that can be downloaded and run as a simulation. Sometime this summer, it's my hope that you can download Gerber files for circuit boards of early working implementations.
In the meantime there is a LOT do do, and I need to scoot for the moment. Happy New Year to each of you.
Marc
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